An integrated circuit chip includes CMOS integrated circuit cells arranged in a semiconductor layer, each including first and second active regions, having first and second polarities, respectively. A first power rail is routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions. A second power rail is routed over second active regions. Global routing channels are routed over the second active regions such that the second power rail is disposed between the global routing channels and the first power rail. The global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.