Invention Grant
US09141426B2 Processor having per core and package level P0 determination functionality
有权
具有每个核心和封装级别P0确定功能的处理器
- Patent Title: Processor having per core and package level P0 determination functionality
- Patent Title (中): 具有每个核心和封装级别P0确定功能的处理器
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Application No.: US13631831Application Date: 2012-09-28
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Publication No.: US09141426B2Publication Date: 2015-09-22
- Inventor: Malini K. Bhandaru , Matthew M. Bace , A Leonard Brown , Ian M. Steiner , Vivek Garg , Eric Dehaemer , Scott P. Bobholz
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/48 ; G06F11/34 ; G06F1/32
Abstract:
A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.
Public/Granted literature
- US20140096137A1 Processor Having Per Core and Package Level P0 Determination Functionality Public/Granted day:2014-04-03
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