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1.
公开(公告)号:US20230185624A1
公开(公告)日:2023-06-15
申请号:US17952120
申请日:2022-09-23
Applicant: Intel Corporation
Inventor: Le Yao , Ruijing Guo , Malini K. Bhandaru , Qiaowei Ren , Haibin Huang , Ruoyu Ying
Abstract: A processing circuitry, a method to be performed at the processing circuitry, a computer-readable storage medium, and a computing system. The processing circuitry is to determine a first mapping between a first set of data parameters and first computing units of a computing network; select, based on the first mapping and on first data having a first workload associated therewith, one or more of the first computing units to execute the first workload, and send for execution the first workload to the one or more of the first computing units; determine a second mapping based on a change in computing units from the first computing units to second computing units, the second mapping between a second set of data parameters and the second computing units; and select, based on the second mapping and on second data having a second workload associated therewith, one or more of the second computing units to execute the second workload.
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公开(公告)号:US11520700B2
公开(公告)日:2022-12-06
申请号:US17042037
申请日:2018-06-29
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Iosif Gasparakis , Sunku Ranganath , Liyong Qiao , Rui Zang , Dakshina Ilangovan , Shaohe Feng , Edwin Verplanke , Priya Autee , Lin A. Yang
IPC: G06F12/08 , G06F9/50 , G06F9/54 , G06F12/0806
Abstract: A holistic view of cache class of service (CLOS) to include an allocation of processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.
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3.
公开(公告)号:US20160085293A1
公开(公告)日:2016-03-24
申请号:US14960693
申请日:2015-12-07
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中,多核处理器包括可独立执行指令的核心,每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。
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公开(公告)号:US11507643B2
公开(公告)日:2022-11-22
申请号:US16373300
申请日:2019-04-02
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Kapil Sood , Christian Maciocco , Isaku Yamahata , Yunhong Jiang
Abstract: At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to send a unique identifier to a license server, establish a secure channel based on the unique identifier, request a license for activating an appliance from a license server over the secure channel, receive license data from the license server over the secure channel; determine whether the license is valid, and activate the appliance in response to a determination that the license data is valid.
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公开(公告)号:US10554574B2
公开(公告)日:2020-02-04
申请号:US14752733
申请日:2015-06-26
Applicant: INTEL CORPORATION
Inventor: Malini K. Bhandaru , Yunhong Jiang
IPC: H04L12/911
Abstract: Resource management techniques for heterogeneous resource clouds are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is implemented in hardware, the logic to comprise an administration component to maintain a cloud resource information database for a heterogeneous resource cloud and an allocation component to generate an ordered unified feature list based on feature preference information associated with a request for a virtual appliance service, iteratively prune an available resource pool of the heterogeneous resource cloud based on the ordered unified feature list to obtain a candidate resource set, and allocate one or more resources among the candidate resource set to the virtual appliance service. Other embodiments are described and claimed.
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公开(公告)号:US09760155B2
公开(公告)日:2017-09-12
申请号:US14960693
申请日:2015-12-07
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
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公开(公告)号:US20140229750A1
公开(公告)日:2014-08-14
申请号:US13976682
申请日:2012-03-13
Applicant: INTEL CORPORATION
Inventor: Malini K. Bhandaru , Eric J. Dehaemer , Samuel W. Ho , Scott P. Bobholz , Chris Poirier
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
Abstract: A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.
Abstract translation: 一种处理器中每个核心性能状态的方法和装置。 每个核心性能状态(PCPS)是指在不同的电压和/频率点对各个内核的并行运行。 在本发明的一个实施例中,处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。 功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。 通过允许其内核具有每个核心性能状态配置,处理器能够降低其功耗并提高其性能。
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公开(公告)号:US10289814B2
公开(公告)日:2019-05-14
申请号:US14581742
申请日:2014-12-23
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Kapil Sood , Christian Maciocco , Isaku Yamahata , Yunhong Jiang
IPC: G06F21/10
Abstract: At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to send a unique identifier to a license server, establish a secure channel based on the unique identifier, request a license for activating an appliance from a license server over the secure channel, receive license data from the license server over the secure channel; determine whether the license is valid, and activate the appliance in response to a determination that the license data is valid.
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公开(公告)号:US10203741B2
公开(公告)日:2019-02-12
申请号:US15048189
申请日:2016-02-19
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
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公开(公告)号:US20180097809A1
公开(公告)日:2018-04-05
申请号:US15283208
申请日:2016-09-30
Applicant: Intel Corporation
Inventor: Somnath Chakrabarti , Mona Vij , Carlos V. Rozas , Brandon Baker , Vincent R. Scarlata , Malini K. Bhandaru , Ning Sun , Jun Nakajima , Francis X. McKeen , Simon P. Johnson
IPC: H04L29/06
CPC classification number: H04L63/10 , H04L63/08 , H04L63/126 , H04L67/10
Abstract: Particular embodiments described herein provide for receiving a request from a first cloud component in a cloud network, wherein the request is to access a key and the key allows the first cloud component to access located trusted execution environment of a second cloud component in the cloud network and allow the request on the condition that the first cloud component is authenticated. A more specific example includes determining a type for the first cloud component, and comparing the determined type of the first cloud component with a component type associated with the key. The example may also include blocking the request if the determined type of the first cloud component does not match the component type associated with the key.
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