An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.