A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.