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    Method for forming a functionalised guide pattern for a graphoepitaxy method
    3.
    发明授权
    Method for forming a functionalised guide pattern for a graphoepitaxy method 有权

    公开(公告)号：US10923352B2

    公开(公告)日：2021-02-16

    申请号：US16304969

    申请日：2017-05-23

    申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    发明人： Raluca Tiron ,  Nicolas Posseme ,  Xavier Chevalier

    IPC分类号： H01L21/027 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/3105

    摘要： A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.

    Process for the manufacture of a recurrent neural network calculator
    4.
    发明申请
    Process for the manufacture of a recurrent neural network calculator 审中-公开

    公开(公告)号：US20190393412A1

    公开(公告)日：2019-12-26

    申请号：US16430464

    申请日：2019-06-04

    申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

    发明人： Elisa VIANELLO ,  Selina La Barbera ,  Jean-Francois Nodin ,  Raluca Tiron

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： The disclosed process includes the successive stages of providing a substrate comprising a dielectric layer; forming a first layer of block copolymers on a part of the dielectric layer, so that the dielectric layer exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the dielectric layer; removing the first layer of block copolymers; forming a first electrode on the structured dielectric layer; forming a memory layer, of resistive memory type, on the first electrode; forming a second electrode on the memory layer; forming a second layer of block copolymers on a part of the second electrode, so that the second electrode exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the second electrode; and removing the second layer of block copolymers.

    Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers
    6.
    发明授权
    Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers 有权
    使用嵌段共聚物制造包含纳米半导体特征的晶体管的工艺

    公开(公告)号：US09147750B2

    公开(公告)日：2015-09-29

    申请号：US13902793

    申请日：2013-05-25

    申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    发明人： Simeon Morvan ,  Francois Andrieu ,  Raluca Tiron

    IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308

    CPC分类号： H01L29/66568 ,  H01L21/0337 ,  H01L21/3086 ,  H01L29/66545 ,  H01L29/66795

    摘要： A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

    摘要翻译： 一种用于制造一个晶体管的方法，包括半导体区域，包括源极区域，漏极区域和被栅极覆盖的沟道区域，包括：在半导体区域的表面上产生初级蚀刻掩模，所述掩模包含在 至少一个主孔; 在所述主孔中沉积嵌段共聚物，其交替地含有至少第一聚合物区域和第二聚合物区域; 去除一系列第一聚合物结构域或一系列第二聚合物结构域，以便产生含有次级孔的次级掩模; 通过所述次级孔蚀刻所述有源区，以便限定纳米尺度的自对准半导体特征; 在所述自对准半导体特征的表面上产生所述栅极。

    Process for the manufacture of a recurrent neural network calculator
    8.
    发明授权
    Process for the manufacture of a recurrent neural network calculator 有权

    公开(公告)号：US10741757B2

    公开(公告)日：2020-08-11

    申请号：US16430464

    申请日：2019-06-04

    申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

    发明人： Elisa Vianello ,  Selina La Barbera ,  Jean-Francois Nodin ,  Raluca Tiron

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： The disclosed process includes the successive stages of providing a substrate comprising a dielectric layer; forming a first layer of block copolymers on a part of the dielectric layer, so that the dielectric layer exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the dielectric layer; removing the first layer of block copolymers; forming a first electrode on the structured dielectric layer; forming a memory layer, of resistive memory type, on the first electrode; forming a second electrode on the memory layer; forming a second layer of block copolymers on a part of the second electrode, so that the second electrode exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the second electrode; and removing the second layer of block copolymers.