公开(公告)号：US09147750B2

公开(公告)日：2015-09-29

申请号：US13902793

申请日：2013-05-25

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Simeon Morvan ,  Francois Andrieu ,  Raluca Tiron

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L29/66568 ,  H01L21/0337 ,  H01L21/3086 ,  H01L29/66545 ,  H01L29/66795

Abstract: A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

Abstract translation: 一种用于制造一个晶体管的方法，包括半导体区域，包括源极区域，漏极区域和被栅极覆盖的沟道区域，包括：在半导体区域的表面上产生初级蚀刻掩模，所述掩模包含在 至少一个主孔; 在所述主孔中沉积嵌段共聚物，其交替地含有至少第一聚合物区域和第二聚合物区域; 去除一系列第一聚合物结构域或一系列第二聚合物结构域，以便产生含有次级孔的次级掩模; 通过所述次级孔蚀刻所述有源区，以便限定纳米尺度的自对准半导体特征; 在所述自对准半导体特征的表面上产生所述栅极。

公开(公告)号：US08853023B2

公开(公告)日：2014-10-07

申请号：US13753436

申请日：2013-01-29

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Simeon Morvan ,  Francois Andrieu ,  Jean-Charles Barbe

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/762 ,  H01L21/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/02107 ,  H01L21/76232 ,  H01L22/12 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78684

Abstract: A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy SixGey with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy SixGey over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy SixGey. In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.

Abstract translation: 一种用于在具有图案表面的图案上应力的方法，该半导体材料层可以是在衬底的表面上产生的层叠层的表面上的硅，所述堆叠包括至少一个合金SixGey与x的应力层 并且y是摩尔分数，以及氧化硅的掩埋层，包括：在尺寸大于所述图案表面的表面的周边，在氧化硅的掩埋层和合金SixGey层的一部分深度处蚀刻 所述合金层; 氧化硅的掩埋层位于所述半导体材料层和合金SixGey的所述应力层之间。 在晶体管结构中，在所述表面的周边处的蚀刻获得如此限定的图案，其尺寸大于位于晶体管栅极之下的感兴趣区域。