Invention Grant
US09171626B2 Memory devices and programming memory arrays thereof 有权
存储器件及其编程存储器阵列

Memory devices and programming memory arrays thereof
Abstract:
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
Public/Granted literature
Information query
Patent Agency Ranking
0/0