Invention Grant
US09172242B2 Electrostatic discharge protection for three dimensional integrated circuit 有权
静电放电保护用于三维集成电路

Electrostatic discharge protection for three dimensional integrated circuit
Abstract:
The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, the trigger line controlling the power of a power clamp in each respective die, a dedicated electrostatic discharge (ESD) line for each respective die, and an ESD detection circuit connected to the dedicated ESD line and to a first power line common to the other dies. When an input signal is received by the ESD detection circuit of one of the plural dies, the ESD detection circuit generates an output signal to the common trigger line to supply power to the power clamp in each of the plural dies to clamp ESD voltage or current to the common first power line or a second power line.
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