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    ESD hard backend structures in nanometer dimension
    2.
    发明授权
    ESD hard backend structures in nanometer dimension 有权

    公开(公告)号：US10170461B2

    公开(公告)日：2019-01-01

    申请号：US15271272

    申请日：2016-09-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jen-Chou Tseng ,  Ming-Fu Tsai ,  Tzu-Heng Chang

    IPC: G01R31/00 ,  H01L27/02 ,  G01R31/26 ,  H01L21/66 ,  H01L23/498 ,  H01L23/525

    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.

    ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION
    3.
    发明申请
    ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION 审中-公开

    公开(公告)号：US20190109129A1

    公开(公告)日：2019-04-11

    申请号：US16202403

    申请日：2018-11-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jen-Chou Tseng ,  Ming-Fu Tsai ,  Tzu-Heng Chang

    IPC: H01L27/02 ,  H01L23/498 ,  G01R31/00 ,  H01L21/66 ,  G01R31/26 ,  H01L23/525

    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.

    Electrostatic discharge protection for three dimensional integrated circuit
    5.
    发明授权
    Electrostatic discharge protection for three dimensional integrated circuit 有权
    静电放电保护用于三维集成电路

    公开(公告)号：US09172242B2

    公开(公告)日：2015-10-27

    申请号：US13667072

    申请日：2012-11-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

    IPC: H02H9/00 ,  H02H9/04

    CPC classification number: H02H9/046 ,  H01L23/552 ,  H01L27/0248 ,  H01L27/04 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15311 ,  H02H3/202

    Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, the trigger line controlling the power of a power clamp in each respective die, a dedicated electrostatic discharge (ESD) line for each respective die, and an ESD detection circuit connected to the dedicated ESD line and to a first power line common to the other dies. When an input signal is received by the ESD detection circuit of one of the plural dies, the ESD detection circuit generates an output signal to the common trigger line to supply power to the power clamp in each of the plural dies to clamp ESD voltage or current to the common first power line or a second power line.

    Abstract translation: 本公开提供了具有多个管芯的三维集成电路。 每个管芯包括与其他管芯共同的触发线，触发线控制每个相应管芯中的电源钳的功率，每个相应管芯的专用静电放电（ESD）线以及连接到专用ESD的ESD检测电路 线和另一个模具共同的第一个电源线。 当由多个管芯中的一个的ESD检测电路接收输入信号时，ESD检测电路产生到公共触发线的输出信号，以向多个管芯中的每一个中的功率钳夹提供电力以钳位ESD电压或电流 到公共第一电力线或第二电力线。

    ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION
    8.
    发明申请
    ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION 审中-公开

    公开(公告)号：US20200219868A1

    公开(公告)日：2020-07-09

    申请号：US16817984

    申请日：2020-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jen-Chou Tseng ,  Ming-Fu Tsai ,  Tzu-Heng Chang

    IPC: H01L27/02 ,  H01L23/525 ,  H01L23/498 ,  H01L21/66 ,  G01R31/26 ,  G01R31/00

    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.

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