公开(公告)号：US11557586B2

公开(公告)日：2023-01-17

申请号：US16987294

申请日：2020-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/02 ,  H01L27/088

Abstract: A device includes standard cells in a layout of an integrated circuit, the standard cells includes first and second standard cells sharing a first active region and a second active region. The first standard cell includes first and second gates. The first gate includes a first gate finger and a second gate finger that are arranged over the first active region, for forming the first transistor and the second transistor. The second gate is separate from the first gate, the second gate includes a third gate finger and a fourth gate finger that are arranged over the second active region, for forming the third transistor and the fourth transistor. The second standard cell includes a third gate arranged over the first active region and the second active region, for forming the fifth transistor and the sixth transistor. The first to fourth transistors operate as an electrostatic discharge protection circuit.

公开(公告)号：US09245878B2

公开(公告)日：2016-01-26

申请号：US14251670

申请日：2014-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0262

Abstract: An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

Abstract translation: ESD保护电路至少包括第一和第二可控硅整流器（SCR）电路。 第一SCR电路耦合在焊盘和正电源端子之间。 第二SCR电路耦合在焊盘和接地端子之间。 SCR电路中的至少一个被配置为选择性地在焊盘和正电源端子和接地端子之一之间提供短路或相对导电的电路径。

公开(公告)号：US09130008B2

公开(公告)日：2015-09-08

申请号：US13778369

申请日：2013-02-27

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chun-Yu Lin ,  Ming-Dou Ker ,  Ming Hsien Tsai ,  Li-Wei Chu ,  Ming-Hsiang Song

IPC: H01L29/66 ,  H01L29/74 ,  H01L29/10

CPC classification number: H01L29/87 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane.

Abstract translation: 一些实施例涉及可控硅整流器（SCR），其包括将SCR阳极耦合到SCR阴极的电流路径。 电流路径包括耦合到SCR阳极的第一垂直电流通路部件和耦合到SCR阴极的第二垂直电流通路部件。 水平电流路径分量包括在沿着第一平面的接合处相遇的第一阱区域和第二阱区域。 第一和第二阱区域协同地跨越第一和第二垂直电流路径部件之间的距离。 第一和第二垂直电流路径部件围绕第一平面对称地相互镜像。

公开(公告)号：US11562996B2

公开(公告)日：2023-01-24

申请号：US16987292

申请日：2020-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/02 ,  H01L27/088

Abstract: A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.

公开(公告)号：US11935885B2

公开(公告)日：2024-03-19

申请号：US18066060

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0274 ,  H01L27/0207 ,  H01L27/0266 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/0886

Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

公开(公告)号：US09172242B2

公开(公告)日：2015-10-27

申请号：US13667072

申请日：2012-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC: H02H9/00 ,  H02H9/04

CPC classification number: H02H9/046 ,  H01L23/552 ,  H01L27/0248 ,  H01L27/04 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15311 ,  H02H3/202

Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, the trigger line controlling the power of a power clamp in each respective die, a dedicated electrostatic discharge (ESD) line for each respective die, and an ESD detection circuit connected to the dedicated ESD line and to a first power line common to the other dies. When an input signal is received by the ESD detection circuit of one of the plural dies, the ESD detection circuit generates an output signal to the common trigger line to supply power to the power clamp in each of the plural dies to clamp ESD voltage or current to the common first power line or a second power line.

Abstract translation: 本公开提供了具有多个管芯的三维集成电路。 每个管芯包括与其他管芯共同的触发线，触发线控制每个相应管芯中的电源钳的功率，每个相应管芯的专用静电放电（ESD）线以及连接到专用ESD的ESD检测电路 线和另一个模具共同的第一个电源线。 当由多个管芯中的一个的ESD检测电路接收输入信号时，ESD检测电路产生到公共触发线的输出信号，以向多个管芯中的每一个中的功率钳夹提供电力以钳位ESD电压或电流 到公共第一电力线或第二电力线。

公开(公告)号：US20150228770A1

公开(公告)日：2015-08-13

申请号：US13778369

申请日：2013-02-27

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chun-Yu Lin ,  Ming-Dou Ker ,  Ming Hsien Tsai ,  Li-Wei Chu ,  Ming-Hsiang Song

IPC: H01L29/74 ,  H01L29/10

CPC classification number: H01L29/87 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/0692

Abstract: Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane.

Abstract translation: 一些实施例涉及可控硅整流器（SCR），其包括将SCR阳极耦合到SCR阴极的电流路径。 电流路径包括耦合到SCR阳极的第一垂直电流通路部件和耦合到SCR阴极的第二垂直电流通路部件。 水平电流路径分量包括在沿着第一平面的接合处相遇的第一阱区域和第二阱区域。 第一和第二阱区域协同地跨越第一和第二垂直电流路径部件之间的距离。 第一和第二垂直电流路径部件围绕第一平面对称地相互镜像。

公开(公告)号：US10741543B2

公开(公告)日：2020-08-11

申请号：US16105494

申请日：2018-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/02 ,  H01L27/088

Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.

公开(公告)号：US09979186B2

公开(公告)日：2018-05-22

申请号：US14920943

申请日：2015-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC: H02H9/04 ,  H01L23/552 ,  H01L27/04 ,  H02H3/20 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L23/552 ,  H01L27/0248 ,  H01L27/04 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15311 ,  H02H3/202

Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line.