Invention Grant
US09174836B2 Integrated bondline spacers for wafer level packaged circuit devices
有权
用于晶圆级封装电路器件的集成接合线间隔物
- Patent Title: Integrated bondline spacers for wafer level packaged circuit devices
- Patent Title (中): 用于晶圆级封装电路器件的集成接合线间隔物
-
Application No.: US14456156Application Date: 2014-08-11
-
Publication No.: US09174836B2Publication Date: 2015-11-03
- Inventor: Roland Gooch , Buu Diep , Thomas Allan Kocian , Stephen H. Black , Adam M. Kennedy
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: RAYTHEON COMPANY
- Current Assignee: RAYTHEON COMPANY
- Current Assignee Address: US MA Waltham
- Agency: Cantor Colburn LLP
- Main IPC: H01L23/12
- IPC: H01L23/12 ; B81B7/00 ; B81C1/00 ; H01L23/053 ; H01L23/00

Abstract:
A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
Public/Granted literature
- US20140346643A1 INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES Public/Granted day:2014-11-27
Information query
IPC分类: