Invention Grant
US09176895B2 Increased error correction for cache memories through adaptive replacement policies
有权
通过自适应替换策略增加高速缓存存储器的纠错
- Patent Title: Increased error correction for cache memories through adaptive replacement policies
- Patent Title (中): 通过自适应替换策略增加高速缓存存储器的纠错
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Application No.: US13844819Application Date: 2013-03-16
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Publication No.: US09176895B2Publication Date: 2015-11-03
- Inventor: Xavier Vera , Javier Carretero Casado , Enric Herrero Abellanas , Daniel Sanchez , Nicholas Axelos , Tanausu Ramirez
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/12
- IPC: G06F12/12 ; G06F12/08 ; G06F11/00
Abstract:
A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.
Public/Granted literature
- US20140281261A1 INCREASED ERROR CORRECTION FOR CACHE MEMORIES THROUGH ADAPTIVE REPLACEMENT POLICIES Public/Granted day:2014-09-18
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