A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.