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公开(公告)号：US09564225B2
公开(公告)日：2017-02-07
申请号：US14878902
申请日：2015-10-08
Applicant: Rambus Inc.
Inventor： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
CPC classification number: G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。
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公开(公告)号：US20140247656A1
公开(公告)日：2014-09-04
申请号：US14145962
申请日：2014-01-01
Applicant: Rambus Inc.
Inventor： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
CPC classification number: G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。
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公开(公告)号：US20160027515A1
公开(公告)日：2016-01-28
申请号：US14878902
申请日：2015-10-08
Applicant: Rambus Inc.
Inventor： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
CPC classification number: G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。
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公开(公告)号：US09177655B2
公开(公告)日：2015-11-03
申请号：US14145962
申请日：2014-01-01
Applicant: Rambus Inc.
Inventor： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
CPC classification number: G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。
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