Invention Grant
US09178688B2 Receiver with clock recovery circuit and adaptive sample and equalizer timing
有权
接收器具有时钟恢复电路和自适应采样和均衡器时序
- Patent Title: Receiver with clock recovery circuit and adaptive sample and equalizer timing
- Patent Title (中): 接收器具有时钟恢复电路和自适应采样和均衡器时序
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Application No.: US14014047Application Date: 2013-08-29
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Publication No.: US09178688B2Publication Date: 2015-11-03
- Inventor: Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Silicon Edge Law Group LLP
- Agent Arthur J. Behiel
- Main IPC: H03K5/159
- IPC: H03K5/159 ; H04L7/033 ; H04L7/00 ; H04L25/03

Abstract:
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Public/Granted literature
- US20140169438A1 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing Public/Granted day:2014-06-19
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