Invention Grant
US09178688B2 Receiver with clock recovery circuit and adaptive sample and equalizer timing 有权
接收器具有时钟恢复电路和自适应采样和均衡器时序

Receiver with clock recovery circuit and adaptive sample and equalizer timing
Abstract:
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
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