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公开(公告)号：US11539556B2
公开(公告)日：2022-12-27
申请号：US17400945
申请日：2021-08-12
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L25/03 , H01J37/00 , H01L21/311 , H01L21/67 , H01L21/683 , H01L21/768 , H01L29/66
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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公开(公告)号：US10050771B2
公开(公告)日：2018-08-14
申请号：US15677467
申请日：2017-08-15
申请人： Rambus Inc.
发明人： Masum Hossain , Brian Leibowitz , Jihong Ren
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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公开(公告)号：US20180083642A1
公开(公告)日：2018-03-22
申请号：US15667184
申请日：2017-08-02
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K5/1565 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
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公开(公告)号：US20180054293A1
公开(公告)日：2018-02-22
申请号：US15677467
申请日：2017-08-15
申请人： Rambus Inc.
发明人： Masum HOSSAIN , Brian Leibowitz , Jihong Ren
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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公开(公告)号：US09397823B2
公开(公告)日：2016-07-19
申请号：US14518061
申请日：2014-10-20
申请人： Rambus Inc.
发明人： Jared Zerbe , Teva Stone , Jihong Ren
IPC分类号： H04L7/02 , H03K5/1252 , H03L7/00
CPC分类号： H04L7/02 , H03K5/1252 , H03L7/00
摘要： A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
摘要翻译： 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。
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公开(公告)号：US20150036732A1
公开(公告)日：2015-02-05
申请号：US14462561
申请日：2014-08-19
申请人： Rambus Inc.
发明人： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
摘要： A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.
摘要翻译： 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择以确定接收到的数据值。
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7.发明申请Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing 有权具有时钟恢复电路和自适应采样和均衡器时序的接收器公开(公告)号：US20140169438A1
公开(公告)日：2014-06-19
申请号：US14014047
申请日：2013-08-29
申请人： Rambus Inc.
发明人： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译： 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。
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8.发明申请METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 有权用于设备之间的通道均衡化的不对称分配的方法和电路公开(公告)号：US20140153631A1
公开(公告)日：2014-06-05
申请号：US13911363
申请日：2013-06-06
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译： 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。
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公开(公告)号：US20190007189A1
公开(公告)日：2019-01-03
申请号：US16032616
申请日：2018-07-11
申请人： Rambus Inc.
发明人： Masum HOSSAIN , Brian Leibowitz , Jihong Ren
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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10.发明授权公开(公告)号：US10135647B2
公开(公告)日：2018-11-20
申请号：US15878149
申请日：2018-01-23
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC分类号： H04L25/03
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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