Invention Grant
US09208120B2 Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect 有权
多处理器,多域,多协议缓存一致猜测共享内存控制器和互连

Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
Abstract:
This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
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