Invention Grant
US09213656B2 Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems 有权
多核系统中多端点原子访问的灵活仲裁方案

Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
Abstract:
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
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