Invention Grant
- Patent Title: Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
- Patent Title (中): 多核系统中多端点原子访问的灵活仲裁方案
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Application No.: US14061470Application Date: 2013-10-23
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Publication No.: US09213656B2Publication Date: 2015-12-15
- Inventor: Kai Chirca , Matthew D Pierson
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/16 ; G06F11/10

Abstract:
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
Public/Granted literature
- US20140143486A1 FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS Public/Granted day:2014-05-22
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