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公开(公告)号：US09304954B2
公开(公告)日：2016-04-05
申请号：US14031567
申请日：2013-09-19
Applicant: Texas Instruments Incorporated
Inventor： Daniel B Wu , Matthew D Pierson , Kai Chirca
CPC classification number: G06F12/0831 , G06F12/0815 , G06F13/1689 , G06F13/4013 , G06F13/4027 , G06F2212/6042 , G06F2212/621
Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.
Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器使用的端点视图，并且可以对每个处理器的事务执行适当的端序转换，以使交易与互连使用的端点视图相适应。
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2.发明申请FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS 审中-公开用于多系统中多端点原子访问的灵活仲裁方案公开(公告)号：US20160062887A1
公开(公告)日：2016-03-03
申请号：US14937945
申请日：2015-11-11
Applicant: Texas Instruments Incorporated
Inventor： Kai Chirca , Matthew D Pierson
CPC classification number: G06F12/084 , G06F3/061 , G06F3/064 , G06F3/0683 , G06F11/1064 , G06F13/1652 , G06F13/1668 , G06F2212/1016 , G06F2212/60
Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace)in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个缓存行访问分配两个连续的插槽，以自动保证单个高速缓存行内所有事务的原子性。 消除了对特定SRAM的所有存储体之间同步的需要，因为通过分配背靠背槽来实现同步。
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3.发明申请Hazard Detection and Elimination for Coherent Endpoint Allowing Out-of-Order Execution 有权相关端点的危害检测和消除允许无序执行公开(公告)号：US20140115267A1
公开(公告)日：2014-04-24
申请号：US14059774
申请日：2013-10-22
Applicant: Texas Instruments Incorporated
Inventor： Matthew D Pierson , Kai Chirca
IPC: G06F12/08
CPC classification number: G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is compared against the address of all entries in the queue. This check is made when the access is ready to transmit to the memory. If there is no address match, then the current access does not conflict with any pending access. If there is an address match, the current access is stalled. The multi-core shared memory controller would then typically proceed to another access waiting a slot to the endpoint memory. Stored addresses in the coherence maintenance address queue are retired when the endpoint memory reports completion of the operation. At this point the access is no longer a hazard to following operations.
Abstract translation: 一致性维护地址队列跟踪从收到的每个内存访问，直到内存报告访问完成。 将每个新访问的地址与队列中所有条目的地址进行比较。 当访问准备好传输到内存时进行此检查。 如果没有地址匹配，则当前访问不会与任何未决访问冲突。 如果地址匹配，则当前访问被停止。 然后，多核共享存储器控制器将通常进行到等待端口存储器的时隙的另一访问。 当端点存储器报告操作完成时，相干维护地址队列中存储的地址将被停用。 在这一点上，访问不再对以下操作构成危害。
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公开(公告)号：US09465767B2
公开(公告)日：2016-10-11
申请号：US14931406
申请日：2015-11-03
Applicant: Texas Instruments Incorporated
Inventor： Kai Chirca , Matthew D Pierson , Daniel B Wu , Timothy D Anderson
CPC classification number: G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
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5.发明授权公开(公告)号：US09465741B2
公开(公告)日：2016-10-11
申请号：US14056729
申请日：2013-10-17
Applicant: Texas Instruments Incorporated
Inventor： Kai Chirca , Daniel B Wu , Matthew D Pierson , Timothy D. Anderson
CPC classification number: G06F12/0831 , G06F12/0815 , G06F13/1689 , G06F13/4013 , G06F13/4027 , G06F2212/6042 , G06F2212/621
Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.
Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器所使用的总线协议，并且可以对每个处理器的事务执行适当的协议转换，以使交易与互连使用的总线协议相适应。
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Patent Agency Ranking
公开(公告)号：US10037439B2
公开(公告)日：2018-07-31
申请号：US14062002
申请日：2013-10-24
Applicant: Texas Instruments Incorporated
Inventor： Timothy D Anderson , Joseph R. M. Zbiciak , Matthew D Pierson , Kai Chirca
IPC: G06F21/78 , G06F12/0815 , G06F21/79 , G06F12/14 , G06F12/0831 , G06F13/16 , H04L29/06 , G06F13/42 , G06F12/0817 , G06F12/1081 , G06F13/28 , G06F13/40 , G06F12/0842
CPC classification number: G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.
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公开(公告)号：US09424193B2
公开(公告)日：2016-08-23
申请号：US14937945
申请日：2015-11-11
Applicant: Texas Instruments Incorporated
Inventor： Kai Chirca , Matthew D Pierson
CPC classification number: G06F12/084 , G06F3/061 , G06F3/064 , G06F3/0683 , G06F11/1064 , G06F13/1652 , G06F13/1668 , G06F2212/1016 , G06F2212/60
Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
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8.发明授权Optimum cache access scheme for multi endpoint atomic access in a multicore system 有权用于多核系统中多端点原子访问的最佳缓存访问方案公开(公告)号：US09372796B2
公开(公告)日：2016-06-21
申请号：US14061494
申请日：2013-10-23
Applicant: Texas Instruments Incorporated
Inventor： Kai Chirca , Matthew D Pierson
CPC classification number: G06F12/0815 , G06F12/0862 , G06F13/1626 , G06F13/1663 , G06F13/1684
Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.
Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个高速缓存行访问分配的两个连续插槽总是处于相同的方向，以获得最大访问速率。
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公开(公告)号：US09298665B2
公开(公告)日：2016-03-29
申请号：US14060192
申请日：2013-10-22
Applicant: Texas Instruments Incorporated
Inventor： Matthew D Pierson , Kai Chirca
CPC classification number: G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
Abstract translation: 本发明优化了非共享访问，避免了相干端点之间的依赖关系，即使在共享时也能确保系统的带宽。 相干控制器分布在所有相干端点上。 每个存储器端点的相干控制器保持每个相干访问的状态，以确保事件的正确排序。 本发明的一致性控制器使用先入先出分配来确保资源的充分利用在停止和简单实现之前。 相干控制器提供每个内存端点的Snoop命令/响应ID分配。
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10.发明申请Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect 审中-公开多处理器，多域，多协议缓存相干投机意识共享内存控制器和互连公开(公告)号：US20160055096A1
公开(公告)日：2016-02-25
申请号：US14931406
申请日：2015-11-03
Applicant: Texas Instruments Incorporated
Inventor： Kai Chirca , Matthew D Pierson , Daniel B Wu , Timothy D Anderson
CPC classification number: G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
Abstract translation: 本发明结合了多核共享存储器控制器和异步协议转换桥以创建非常有效的异构多处理器系统。 在通过协议转换网桥之后，命令行进通过常规处理器端口。 这允许互连保持不变，同时连接不同处理器的任何组合。 本发明将所有处理器紧密地集成到相同的存储器控制器/互连中。
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