This disclosure provides systems, methods and apparatus for an all n-type transistor inverter circuit. A circuit can include an input thin film transistor (TFT), a pull-down TFT, a discharge TFT, a first pull-up TFT, a second pull-up TFT, and a floating capacitor. The circuit also can include first and second low-voltage voltage sources and first and second high-voltage voltage sources. The TFTs, the capacitor, and the voltage sources can be coupled such that an output of the circuit is the logical opposite of an input of the circuit. In some implementations, the circuit can exhibit zero DC current in both logic states and can output voltages substantially equal to the voltage output by the first low-voltage voltage source and the second high-voltage voltage source. In some implementations, the circuit can be used to construct D flip-flops, buffers, and controllers for an active matrix electronic display.