Invention Grant
- Patent Title: Chip arrangement, and method for forming a chip arrangement
- Patent Title (中): 芯片布置，以及形成芯片布置的方法
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Application No.: US13892367Application Date: 2013-05-13
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Publication No.: US09219031B2Publication Date: 2015-12-22
- Inventor: Peter Ossimitz , Robert Bauer , Tobias Jacobs
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: INFINEON TECHNOLOGIES AG
- Current Assignee: INFINEON TECHNOLOGIES AG
- Current Assignee Address: DE Neubiberg
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/768 ; H01L23/00 ; H01L23/14 ; H01L23/15
Abstract:
A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.
Public/Granted literature
- US20140332953A1 CHIP ARRANGEMENT, AND METHOD FOR FORMING A CHIP ARRANGEMENT Public/Granted day:2014-11-13
Information query
IPC分类:
