公开(公告)号：US20180061742A1

公开(公告)日：2018-03-01

申请号：US15685880

申请日：2017-08-24

Applicant: Infineon Technologies AG

Inventor： Sergey Ananiev ,  Robert Bauer ,  Heinrich Koerner ,  Yik Yee Tan ,  Juergen Walter

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/484 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/85365 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure.

公开(公告)号：US20140332953A1

公开(公告)日：2014-11-13

申请号：US13892367

申请日：2013-05-13

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Robert Bauer ,  Tobias Jacobs

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2924/0002 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01047

Abstract: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.

Abstract translation: 芯片布置可以包括：包括多个电网的芯片，其中每个电网包括至少一个焊盘; 以及形成在所述多个电网中的大多数的所述至少一个焊盘上的多个柱，其中所述多个柱可以被配置为将所述多个电网中的大多数的所述至少一个焊盘连接到 芯片外部连接区域。

公开(公告)号：US09219031B2

公开(公告)日：2015-12-22

申请号：US13892367

申请日：2013-05-13

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Robert Bauer ,  Tobias Jacobs

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2924/0002 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01047

Abstract: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.

Abstract translation: 芯片布置可以包括：包括多个电网的芯片，其中每个电网包括至少一个接合焊盘; 以及形成在所述多个电网中的大多数的所述至少一个焊盘上的多个柱，其中所述多个柱可以被配置为将所述多个电网中的大多数的所述至少一个焊盘连接到 芯片外部连接区域。