Invention Grant
US09219128B2 Methods of fabricating bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance
有权
制造具有减小的外延基极面的双极结型晶体管的方法对低寄生电极基极电容的影响
- Patent Title: Methods of fabricating bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance
- Patent Title (中): 制造具有减小的外延基极面的双极结型晶体管的方法对低寄生电极基极电容的影响
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Application No.: US13800091Application Date: 2013-03-13
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Publication No.: US09219128B2Publication Date: 2015-12-22
- Inventor: Renata Camillo-Castillo , David L. Harame , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L29/73
- IPC: H01L29/73 ; H01L29/66 ; H01L21/8249 ; H01L29/732 ; H01L29/737 ; H01L29/08 ; H01L29/10 ; H01L21/762
Abstract:
Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.
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