公开(公告)号：US20170278955A1

公开(公告)日：2017-09-28

申请号：US15081443

申请日：2016-03-25

申请人： GLOBALFOUNDRIES INC.

发明人： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC分类号： H01L29/732 ,  H01L21/762 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/732 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/73

摘要： Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US10170553B2

公开(公告)日：2019-01-01

申请号：US15626241

申请日：2017-06-19

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC分类号： H01L29/423 ,  H01L29/732 ,  H01L21/306 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/10

摘要： Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

公开(公告)号：US20170221888A1

公开(公告)日：2017-08-03

申请号：US15010189

申请日：2016-01-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Xusheng WU ,  Qizhi LIU ,  David HARAME ,  Renata Camillo-Castillo

IPC分类号： H01L27/088 ,  H01L21/311 ,  H01L21/324 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L21/324 ,  H01L21/823821 ,  H01L21/823892

摘要： A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

公开(公告)号：US09722057B2

公开(公告)日：2017-08-01

申请号：US14747668

申请日：2015-06-23

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Vibhor Jain ,  Marwan H. Khater

IPC分类号： H01L29/737 ,  H01L21/265 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7371 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732

摘要： Device structure and fabrication methods for a bipolar junction transistor. A trench isolation region is formed that bounds an active device region along a sidewall. A dielectric region is formed that extends laterally from the sidewall of the active device region into the active device region. The dielectric region is located beneath a top surface of the active device region such that a section of the active device region is located between the top surface and the dielectric region.

公开(公告)号：US09721949B1

公开(公告)日：2017-08-01

申请号：US15010189

申请日：2016-01-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Xusheng Wu ,  Qizhi Liu ,  David Harame ,  Renata Camillo-Castillo

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L21/308 ,  H01L21/311

CPC分类号： H01L21/324 ,  H01L21/823821 ,  H01L21/823892

摘要： A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

公开(公告)号：US20160372582A1

公开(公告)日：2016-12-22

申请号：US14745704

申请日：2015-06-22

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/732

CPC分类号： H01L29/0821 ,  H01L21/762 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7371

摘要： Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

摘要翻译： 使用包括高电阻处理晶片的绝缘体上硅衬底形成器件结构和器件结构的方法。 在高电阻处理晶片中形成掺杂区域。 形成第一沟槽，其延伸穿过绝缘体上硅衬底的器件层和掩埋绝缘体层到高电阻处理晶片。 掺杂区域包括在第一沟槽横向延伸的掺杂区域的横向延伸。 半导体层在第一沟槽内外延生长，并且使用半导体层的至少一部分形成器件结构。 形成第二沟槽，其延伸穿过器件层和掩埋绝缘体层到掺杂区域的横向延伸，并且在第二沟槽中形成导电插塞。 掺杂区域和插塞包括身体接触。

公开(公告)号：US09318551B2

公开(公告)日：2016-04-19

申请号：US14527042

申请日：2014-10-29

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Marwan H. Khater

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/735 ,  H01L29/737

摘要： Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.

公开(公告)号：US10446644B2

公开(公告)日：2019-10-15

申请号：US14745704

申请日：2015-06-22

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/732

摘要： Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

公开(公告)号：US10014397B1

公开(公告)日：2018-07-03

申请号：US15383171

申请日：2016-12-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Vibhor Jain ,  Qizhi Liu ,  David L. Harame ,  Renata Camillo-Castillo

IPC分类号： H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/265 ,  H01L29/735 ,  H01L27/12

摘要： Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

公开(公告)号：US20170288033A1

公开(公告)日：2017-10-05

申请号：US15626241

申请日：2017-06-19

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L21/306

CPC分类号： H01L29/0821 ,  H01L21/30608 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

摘要： Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.