Invention Grant
- Patent Title: Method and apparatus for a zero voltage processor
- Patent Title (中): 零电压处理器的方法和装置
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Application No.: US14496233Application Date: 2014-09-25
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Publication No.: US09223389B2Publication Date: 2015-12-29
- Inventor: Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F12/08 ; G06F11/14 ; G11C7/10

Abstract:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Public/Granted literature
- US20150052377A1 Method And Apparatus For A Zero Voltage Processor Public/Granted day:2015-02-19
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