Invention Grant
US09223389B2 Method and apparatus for a zero voltage processor 有权
零电压处理器的方法和装置

Method and apparatus for a zero voltage processor
Abstract:
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Public/Granted literature
Information query
Patent Agency Ranking
0/0