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    Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain
    7.
    发明授权
    Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain 有权

    公开(公告)号：US10955885B2

    公开(公告)日：2021-03-23

    申请号：US16299019

    申请日：2019-03-11

    Applicant: Intel Corporation

    Inventor： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

    IPC: G06F1/00 ,  G06F1/26 ,  G06F1/3234 ,  G06F1/3287 ,  H03K17/687

    Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

    CHARGE-SAVING POWER-GATE APPARATUS AND METHOD
    8.
    发明申请
    CHARGE-SAVING POWER-GATE APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20180241384A1

    公开(公告)日：2018-08-23

    申请号：US15958768

    申请日：2018-04-20

    Applicant: Intel Corporation

    Inventor： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

    IPC: H03K17/00 ,  H03K17/687

    CPC classification number: H03K17/00 ,  H03K17/687 ,  H03K2217/0036 ,  H03K2217/0063

    Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.

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