Invention Grant
US09229828B2 Mechanism for achieving high memory reliability, availability and serviceability
有权
实现高内存可靠性,可用性和可维护性的机制
- Patent Title: Mechanism for achieving high memory reliability, availability and serviceability
- Patent Title (中): 实现高内存可靠性,可用性和可维护性的机制
-
Application No.: US14563761Application Date: 2014-12-08
-
Publication No.: US09229828B2Publication Date: 2016-01-05
- Inventor: Dableena Das , Kai Cheng , Jonathan C. Jasper
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03M13/05
- IPC: H03M13/05 ; G06F11/10 ; G06F11/20

Abstract:
A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
Public/Granted literature
- US20150220410A1 MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SERVICEABILITY Public/Granted day:2015-08-06
Information query
IPC分类: