公开(公告)号：US09229828B2

公开(公告)日：2016-01-05

申请号：US14563761

申请日：2014-12-08

Applicant: INTEL CORPORATION

Inventor： Dableena Das ,  Kai Cheng ,  Jonathan C. Jasper

IPC: H03M13/05 ,  G06F11/10 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/05

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract translation: 描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。 本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。

公开(公告)号：US20160343453A1

公开(公告)日：2016-11-24

申请号：US15226863

申请日：2016-08-02

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC: G11C29/36 ,  G11C29/18 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/18 ,  G11C29/38 ,  G11C29/44 ,  G11C29/56008

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

公开(公告)号：US08745464B2

公开(公告)日：2014-06-03

申请号：US13968266

申请日：2013-08-15

Applicant: Intel Corporation

Inventor： Ramesh Subashchandrabose ,  Tessil Thomas ,  Sambaran Mitra ,  Debaleena Das ,  Kai Cheng

IPC: H03M13/00 ,  G11C29/00 ,  G06F12/06 ,  H03M13/03 ,  G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H04L1/00 ,  G06F12/02 ,  G11C8/12

CPC classification number: H03M13/03 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1064 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/02 ,  G11C8/12 ,  G11C29/00 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19 ,  H04L1/0061

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract translation: 本公开的实施例描述了用于在存储器系统中提供排名特定循环冗余校验的方法，装置和系统配置。

公开(公告)号：US10241912B2

公开(公告)日：2019-03-26

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/0811 ,  G06F12/0897 ,  G11C11/406 ,  G11C14/00 ,  G06F12/0895

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US10719443B2

公开(公告)日：2020-07-21

申请号：US16363992

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G11C11/406 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US09423959B2

公开(公告)日：2016-08-23

申请号：US13931875

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Richard A. Uhlig ,  Robert S. Chappell ,  Joseph Nuzman ,  Kai Cheng ,  Sailesh Kottapalli ,  Yen-Cheng Liu ,  Mohan Kumar ,  Raj K. Ramanujan ,  Glenn J. Hinton

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

Abstract translation: 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US20140229797A1

公开(公告)日：2014-08-14

申请号：US13997616

申请日：2012-03-30

Applicant: INTEL CORPORATION

Inventor： Rajat Agrawal ,  Debaleena Das ,  Kai Cheng

IPC: H03M13/05

CPC classification number: H03M13/05 ,  G06F11/1064 ,  G06F12/0895 ,  G11C2029/0411 ,  Y02D10/13

Abstract: Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

Abstract translation: 用于利用预留空间进行纠错功能的方法，技术，系统和装置。 当存储器件发生故障时，用于存储纠错码（ECC）数据的多个高速缓存行中的高速缓存行（“保留行”）用于存储与多个高速缓存行中的其它高速缓存行相对应的ECC数据。