公开(公告)号：US09229828B2

公开(公告)日：2016-01-05

申请号：US14563761

申请日：2014-12-08

Applicant: INTEL CORPORATION

Inventor： Dableena Das ,  Kai Cheng ,  Jonathan C. Jasper

IPC: H03M13/05 ,  G06F11/10 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/05

Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.

Abstract translation: 描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。 本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。