Invention Grant
- Patent Title: Dummy patterns and method for generating dummy patterns
- Patent Title (中): 虚拟模式和生成虚拟模式的方法
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Application No.: US14065412Application Date: 2013-10-28
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Publication No.: US09245822B2Publication Date: 2016-01-26
- Inventor: Chen-Hua Tsai , Jian-Cheng Chen , Chin-Yueh Tsai , Yao-Jen Fan , Heng-Kun Chen , Hsiang Yang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: G03F1/36
- IPC: G03F1/36 ; H01L23/48 ; G06F17/50 ; G03F1/70
Abstract:
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.
Public/Granted literature
- US20140042640A1 DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS Public/Granted day:2014-02-13
Information query
