Invention Grant
- Patent Title: Multi-solder techniques and configurations for integrated circuit package assembly
- Patent Title (中): 用于集成电路封装组装的多焊接技术和配置
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Application No.: US14328599Application Date: 2014-07-10
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Publication No.: US09257405B2Publication Date: 2016-02-09
- Inventor: Rajen S. Sidhu , Wei Hu , Carl L. Deppisch , Martha A. Dudek
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H01L23/00 ; B23K35/02 ; H01L23/498 ; H01L21/48 ; H01L23/31
Abstract:
Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20140319682A1 MULTI-SOLDER TECHNIQUES AND CONFIGURATIONS FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY Public/Granted day:2014-10-30
Information query
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