Invention Grant
US09257526B2 Method for manufacturing a vertical bipolar transistor compatible with CMOS manufacturing methods
有权
制造与CMOS制造方法兼容的垂直双极晶体管的方法
- Patent Title: Method for manufacturing a vertical bipolar transistor compatible with CMOS manufacturing methods
- Patent Title (中): 制造与CMOS制造方法兼容的垂直双极晶体管的方法
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Application No.: US14313836Application Date: 2014-06-24
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Publication No.: US09257526B2Publication Date: 2016-02-09
- Inventor: Pierre Boulenc
- Applicant: STMicroelectronics SA
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Agency: Seed IP Law Group PLLC
- Priority: FR1356023 20130624
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8249 ; H01L29/732 ; H01L29/06 ; H01L29/739 ; H01L29/08

Abstract:
The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.
Public/Granted literature
- US20140374792A1 METHOD FOR MANUFACTURING A VERTICAL BIPOLAR TRANSISTOR COMPATIBLE WITH CMOS MANUFACTURING METHODS Public/Granted day:2014-12-25
Information query
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