公开(公告)号：US09257526B2

公开(公告)日：2016-02-09

申请号：US14313836

申请日：2014-06-24

Applicant: STMicroelectronics SA

Inventor： Pierre Boulenc

IPC: H01L29/66 ,  H01L21/8249 ,  H01L29/732 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L29/66333 ,  H01L21/8249 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/7325 ,  H01L29/7395

Abstract: The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.

Abstract translation: 本公开涉及一种用于制造双极晶体管的方法。 该方法形成沟槽以将第一区域与半导体晶片中的第二区域隔离，并将这些区域与晶片的其余部分隔离。 该方法在第二区域中形成第一P掺杂阱，并且在第一区域中通过P掺杂产生第二阱和第三阱的集电极区。 第二个井与沟槽下面的第一个井接触。 该方法还在集电极区域和晶片表面上产生N掺杂的基极阱，并在第一区域上形成CMOS晶体管栅极并限定第三区域和第四区域。 该方法还在第一阱中形成P +掺杂的集电极接触区，在第三区中形成P +掺杂的发射极区，并在第四区中形成N +掺杂的基极接触区。