Invention Grant
- Patent Title: Handle wafer for high resistivity trap-rich SOI
- Patent Title (中): 处理高电阻阱富集SOI的晶圆
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Application No.: US14222785Application Date: 2014-03-24
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Publication No.: US09269591B2Publication Date: 2016-02-23
- Inventor: Alex Kalnitsky , Chung-Long Chang , Yung-Chih Tsai , Tsung-Yu Yang , Keng-Yu Chen , Yong-En Syu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L21/322
- IPC: H01L21/322 ; H01L27/12 ; H01L29/34

Abstract:
The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.
Public/Granted literature
- US20150270143A1 HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI Public/Granted day:2015-09-24
Information query
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