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    Handle wafer for high resistivity trap-rich SOI
    3.
    发明授权
    Handle wafer for high resistivity trap-rich SOI 有权
    处理高电阻阱富集SOI的晶圆

    公开(公告)号：US09269591B2

    公开(公告)日：2016-02-23

    申请号：US14222785

    申请日：2014-03-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Alex Kalnitsky ,  Chung-Long Chang ,  Yung-Chih Tsai ,  Tsung-Yu Yang ,  Keng-Yu Chen ,  Yong-En Syu

    IPC分类号： H01L21/322 ,  H01L27/12 ,  H01L29/34

    CPC分类号： H01L21/3226 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/32105 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/34

    摘要： The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

    摘要翻译： 本公开内容涉及具有富集陷阱层的绝缘体上硅（SOI）衬底，其具有设置在处理晶片内的晶体缺陷以及相关联的形成方法。 在一些实施例中，SOI衬底具有处理晶片。 在与处理晶片的顶表面相邻的位置处，在处理晶片内设置具有多个用于捕获载流子的晶体缺陷的富含阱的层。 绝缘层设置在手柄晶片上。 绝缘层具有邻接手柄晶片的顶表面的第一侧和与活性硅薄层邻接的相对的第二侧。 通过在处理晶片内形成富含阱的层，减少了将富含陷阱的材料（例如多晶硅）沉积到处理晶片上的制造成本，并防止了热不稳定性问题。

    Mechanisms for forming radio frequency (RF) area of integrated circuit structure
    6.
    发明授权
    Mechanisms for forming radio frequency (RF) area of integrated circuit structure 有权
    形成集成电路结构射频（RF）区域的机制

    公开(公告)号：US09230988B2

    公开(公告)日：2016-01-05

    申请号：US14068353

    申请日：2013-10-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

    摘要： Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

    摘要翻译： 提供了形成集成电路的射频区域的机构的实施例。 集成电路结构的射频区域包括衬底，在衬底上形成的掩埋氧化物层以及形成在衬底和掩埋氧化物层之间的界面层。 集成电路结构的射频区域还包括形成在掩埋氧化物层上的硅层和形成在深沟槽中的层间电介质层。 集成电路结构的射频区域还包括延伸穿过硅层，掩埋氧化物层和界面层的层间电介质层。 集成电路结构的射频区域包括形成在深沟槽中的层间电介质层下方的注入区域和形成在注入区域下方的多晶硅层。

    HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI
    7.
    发明申请
    HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI 有权
    用于高电阻TRAP-RICH SOI的手柄波形

    公开(公告)号：US20150270143A1

    公开(公告)日：2015-09-24

    申请号：US14222785

    申请日：2014-03-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Alex Kalnitsky ,  Chung-Long Chang ,  Yung-Chih Tsai ,  Tsung-Yu Yang ,  Keng-Yu Chen ,  Yong-En Syu

    IPC分类号： H01L21/322 ,  H01L29/34 ,  H01L27/12

    CPC分类号： H01L21/3226 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/32105 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/34

    摘要： The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

    摘要翻译： 本公开内容涉及具有富集陷阱层的绝缘体上硅（SOI）衬底，其具有设置在处理晶片内的晶体缺陷以及相关联的形成方法。 在一些实施例中，SOI衬底具有处理晶片。 在与处理晶片的顶表面相邻的位置处，在处理晶片内设置具有多个用于捕获载流子的晶体缺陷的富含阱的层。 绝缘层设置在手柄晶片上。 绝缘层具有邻接手柄晶片的顶表面的第一侧和与活性硅薄层邻接的相对的第二侧。 通过在处理晶片内形成富含阱的层，减少了将富含陷阱的材料（例如多晶硅）沉积到处理晶片上的制造成本，并防止了热不稳定性问题。