公开(公告)号：US20250069994A1

公开(公告)日：2025-02-27

申请号：US18945469

申请日：2024-11-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MATERIALS CO., LTD.

Inventor： Akito SASAKI ,  Kentaro IWAI ,  Keita KANAHARA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L29/34

Abstract: A ceramic circuit substrate according to an embodiment includes a ceramic substrate and multiple metal parts. The ceramic substrate includes a first surface. The multiple metal parts are located respectively in multiple first regions of the first surface. The first surface includes a second region positioned between adjacent first regions of the multiple metal parts. An average length RSm of roughness curve elements in the second region is not less than 40 μm. The average length RSm is preferably not more than 100 μm. A maximum peak height Rp of a surface roughness curve in the second region is preferably not less than 1.0 μm. A maximum valley depth Rv of a surface roughness curve in the second region is preferably not less than 1.0 μm.

公开(公告)号：US20240312779A1

公开(公告)日：2024-09-19

申请号：US18677887

申请日：2024-05-30

Applicant: FILNEX INC.

Inventor： Mitsuhiko OGIHARA ,  Akihiro HASHIMOTO

IPC: H01L21/02 ,  H01L21/67 ,  H01L29/34

CPC classification number: H01L21/02444 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/67098 ,  H01L29/34

Abstract: A semiconductor substrate manufacturing method includes the steps of: forming, on a first surface of a first substrate, a plurality of terrace portions arranged in a first direction parallel to a horizontal plane of the first substrate, and a step portion having a predetermined height between two adjacent terrace portions in the first direction; forming a first semiconductor layer such that a part of the step portion is exposed; and vaporizing a portion of Si of the first substrate from a part of the step portion exposed from the first semiconductor layer by performing heat treatment on the first substrate on which the first semiconductor layer is formed, thereby forming a buffer layer having at least one graphene layer in at least a part between the first semiconductor layer and the first substrate.

公开(公告)号：US20240290616A1

公开(公告)日：2024-08-29

申请号：US18435035

申请日：2024-02-07

Applicant: DENSO CORPORATION ,  FUJI ELECTRIC CO., LTD.

Inventor： Tomohiro MIMURA ,  Kensuke HATA ,  Masanobu IWAYA

IPC: H01L21/04 ,  H01L23/34 ,  H01L29/06 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/045 ,  H01L21/046 ,  H01L23/34 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813

Abstract: A silicon carbide semiconductor device has a semiconductor substrate, a trench gate structure disposed in the semiconductor substrate, a first electrode electrically connected to an impurity region and a bae layer of the semiconductor substrate, a second electrode connected to a substrate, and an interlayer insulating film disposed between a gate electrode and the first electrode. The trench gate structure includes a gate insulating film disposed in a trench of the semiconductor substrate and the gate electrode disposed on the gate insulating film. A portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one of nitrogen, hydrogen or phosphorous. The interlayer insulating film has a contact insulating film that is in contact with the gate electrode. The contact insulating film is provided by a deposited film.

公开(公告)号：US12014924B2

公开(公告)日：2024-06-18

申请号：US17258967

申请日：2019-06-14

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Kenji Kanbara ,  Hironori Itoh ,  Tsutomu Hori

IPC: H01L29/36 ,  C30B29/36 ,  H01L21/02 ,  H01L21/04 ,  H01L21/78 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02529 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/046 ,  H01L21/78 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7802

Abstract: When a value obtained by dividing the number of the one or more second regions by a total of the number of the one or more first regions and the number of the one or more second regions is defined as a first defect free area ratio, a value obtained by dividing the number of the one or more fourth regions by a total of the number of the one or more third regions and the number of the one or more fourth regions is defined as a second defect free area ratio, and a value obtained by dividing the number of the one or more macroscopic defects by an area of the central region is defined as X cm−2, A is smaller than B, B is less than or equal to 4, X is more than 0 and less than 4, and a Formula 1 is satisfied.

公开(公告)号：US11948819B2

公开(公告)日：2024-04-02

申请号：US16335059

申请日：2017-06-14

Applicant: SUMCO CORPORATION

Inventor： Keiichiro Mori

IPC: H01L21/67 ,  B24B37/005 ,  G01N21/95 ,  G01N21/956 ,  G01Q60/24 ,  H01L21/66 ,  H01L29/16 ,  H01L29/34

CPC classification number: H01L21/67288 ,  B24B37/005 ,  G01N21/9501 ,  G01N21/956 ,  G01Q60/24 ,  H01L22/24 ,  H01L29/16 ,  H01L29/34

Abstract: Provided is a method of evaluating a silicon wafer, the method including a first determination that determines the presence or absence of an abnormality by inspecting a surface of an evaluation-target silicon wafer with a light scattering type surface inspection device; and a second determination that determines the presence or absence of an abnormality through observing, with an atomic force microscope, a region of the surface of the evaluation-target silicon wafer, where the presence of an abnormality has not been confirmed in the first determination.

公开(公告)号：US11888036B2

公开(公告)日：2024-01-30

申请号：US17848919

申请日：2022-06-24

Applicant: SUMCO CORPORATION

Inventor： Kazuya Kodani ,  Toshiaki Ono ,  Kazuhisa Torigoe

IPC: H01L29/16 ,  H01L29/34 ,  H01L21/02

CPC classification number: H01L29/34 ,  H01L29/16 ,  H01L21/0257

Abstract: A manufacturing method of an epitaxial silicon wafer includes forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film to heat treatment in a nitrogen atmosphere.

公开(公告)号：US11705329B2

公开(公告)日：2023-07-18

申请号：US16620088

申请日：2018-05-14

Applicant: SHOWA DENKO K.K.

Inventor： Koji Kamei

IPC: H01L21/02 ,  C23C16/32 ,  C30B25/20 ,  C30B29/36 ,  H01L29/04 ,  H01L29/16 ,  H01L29/34 ,  C01B32/956 ,  C01B32/90

CPC classification number: H01L21/02529 ,  C01B32/956 ,  C23C16/325 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02428 ,  H01L21/02634 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/34 ,  C01B32/90

Abstract: According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

公开(公告)号：US20230078982A1

公开(公告)日：2023-03-16

申请号：US17976191

申请日：2022-10-28

Applicant: SiCrystal GmbH

Inventor： Bernhard Ecker ,  Ralf Müller ,  Matthias Stockmeier ,  Michael Vogel ,  Arnd-Dietrich Weber

IPC: H01L21/02 ,  C30B29/36 ,  H01L29/04 ,  H01L29/16 ,  H01L29/34 ,  C30B23/02

Abstract: The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

公开(公告)号：US20230071989A1

公开(公告)日：2023-03-09

申请号：US17985112

申请日：2022-11-10

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Zachary GEIGER

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11545449B2

公开(公告)日：2023-01-03

申请号：US16017409

申请日：2018-06-25

Applicant: INTEL CORPORATION

Inventor： Paul A. Nyhus ,  Gurpreet Singh

IPC: H01L23/58 ,  H01L23/00 ,  H01L29/34 ,  H01L21/768 ,  H01L23/31

Abstract: A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.