公开(公告)号：US20230078982A1

公开(公告)日：2023-03-16

申请号：US17976191

申请日：2022-10-28

申请人： SiCrystal GmbH

发明人： Bernhard Ecker ,  Ralf Müller ,  Matthias Stockmeier ,  Michael Vogel ,  Arnd-Dietrich Weber

IPC分类号： H01L21/02 ,  C30B29/36 ,  H01L29/04 ,  H01L29/16 ,  H01L29/34 ,  C30B23/02

摘要： The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

公开(公告)号：US20230071989A1

公开(公告)日：2023-03-09

申请号：US17985112

申请日：2022-11-10

申请人： Intel Corporation

发明人： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Zachary GEIGER

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02

摘要： Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11545449B2

公开(公告)日：2023-01-03

申请号：US16017409

申请日：2018-06-25

申请人： INTEL CORPORATION

发明人： Paul A. Nyhus ,  Gurpreet Singh

IPC分类号： H01L23/58 ,  H01L23/00 ,  H01L29/34 ,  H01L21/768 ,  H01L23/31

摘要： A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.

公开(公告)号：US11532734B2

公开(公告)日：2022-12-20

申请号：US16370449

申请日：2019-03-29

申请人： Intel Corporation

发明人： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Zachary Geiger

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02 ,  H01L29/423

摘要： Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11515140B2

公开(公告)日：2022-11-29

申请号：US16409706

申请日：2019-05-10

申请人： SiCrystal GmbH

发明人： Bernhard Ecker ,  Ralf Müller ,  Matthias Stockmeier ,  Michael Vogel ,  Arnd-Dietrich Weber

IPC分类号： H01L21/02 ,  H01L29/16 ,  H01L29/34 ,  H01L29/04 ,  C30B29/36 ,  C30B23/02

摘要： The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

公开(公告)号：US11437490B2

公开(公告)日：2022-09-06

申请号：US16843262

申请日：2020-04-08

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Sipeng Gu ,  Haiting Wang

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L29/51 ,  H01L21/02 ,  H01L29/34

摘要： One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.

公开(公告)号：US20220157945A1

公开(公告)日：2022-05-19

申请号：US17667201

申请日：2022-02-08

申请人： ROHM CO., LTD.

发明人： Kentaro TAMURA

IPC分类号： H01L29/16 ,  H01L29/872 ,  H01L29/47 ,  H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  C30B25/20 ,  C23C16/32 ,  C30B25/18 ,  C30B29/36 ,  H01L29/34 ,  H01L29/78

摘要： The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with SinHxClyFz (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with CmHqClrFs (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.

公开(公告)号：US11177377B2

公开(公告)日：2021-11-16

申请号：US16726263

申请日：2019-12-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Ming Chang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/34

摘要： A mesa structure includes a substrate. A mesa protrudes out of the substrate. The mesa includes a slope and a top surface. The slope surrounds the top surface. A lattice damage area is disposed at inner side of the slope. The mesa can optionally further includes an insulating layer covering the lattice damage area. The insulating layer includes an oxide layer or a nitride layer.

公开(公告)号：US11171015B2

公开(公告)日：2021-11-09

申请号：US16567290

申请日：2019-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC分类号： H01L21/322 ,  H01L23/66 ,  H01L21/762 ,  H01L29/34 ,  H01L29/06

摘要： In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US20210210602A1

公开(公告)日：2021-07-08

申请号：US17055542

申请日：2019-04-08

申请人： SCIOCS COMPANY LIMITED ,  SUMITOMO CHEMICAL COMPANY, LIMITED

发明人： Takeshi MEGURO ,  Junichiro TAKEDA ,  Hiroyuki TOMIOKA

IPC分类号： H01L29/10 ,  H01L29/34 ,  H01L29/20 ,  H01L29/778

摘要： Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 μm or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.