发明授权
US09276074B2 Methods of fabricating semiconductor devices having buried channel array
有权
制造具有掩埋沟道阵列的半导体器件的方法
- 专利标题: Methods of fabricating semiconductor devices having buried channel array
- 专利标题(中): 制造具有掩埋沟道阵列的半导体器件的方法
-
申请号: US13761376申请日: 2013-02-07
-
公开(公告)号: US09276074B2公开(公告)日: 2016-03-01
- 发明人: Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
- 申请人: Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
- 申请人地址: KR Suwon-Si, Gyeonggi-Do
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: KR Suwon-Si, Gyeonggi-Do
- 代理机构: F. Chau & Associates, LLC
- 优先权: KR10-2012-0045696 20120430
- 主分类号: H01L21/44
- IPC分类号: H01L21/44 ; H01L21/336 ; H01L29/423 ; H01L29/66 ; H01L27/108 ; H01L27/02
摘要:
A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.
公开/授权文献
信息查询
IPC分类: