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    SEMICONDUCTOR DEVICE HAVING LINE-TYPE TRENCH TO DEFINE ACTIVE REGION AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LINE-TYPE TRENCH TO DEFINE ACTIVE REGION AND METHOD OF FORMING THE SAME 有权
    具有线型倾斜的半导体器件定义活性区域及其形成方法

    公开(公告)号：US20140117566A1

    公开(公告)日：2014-05-01

    申请号：US13763927

    申请日：2013-02-11

    申请人： Jay-Bok CHOI ,  Kyu-Hyun LEE ,  Mi-Jeong JANG ,  Young-Jin CHOI ,  Ju-Young HUH

    发明人： Jay-Bok CHOI ,  Kyu-Hyun LEE ,  Mi-Jeong JANG ,  Young-Jin CHOI ,  Ju-Young HUH

    IPC分类号： H01L23/498

    CPC分类号： H01L23/49838 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

    摘要翻译： 半导体器件包括彼此平行的多个平行沟槽，彼此平行的多个相交沟槽，由平行沟槽和交叉沟槽约束的多个有源区域，一个 穿过有源区的多个下导电线，彼此平行的多个上导线，穿过下导电线，并跨越有源区，以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES
    3.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES 审中-公开
    制造半导体器件的方法，包括自对准门极隔离器件隔离开关

    公开(公告)号：US20130115745A1

    公开(公告)日：2013-05-09

    申请号：US13607315

    申请日：2012-09-07

    申请人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Ji-young Kim ,  Jay-bok Choi

    发明人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Ji-young Kim ,  Jay-bok Choi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876

    摘要： Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer.

    摘要翻译： 制造半导体器件的方法可以通过形成包括在第一方向上延伸的多个栅极沟槽和具有开口并且在基板上沿第一方向延伸的模具层的结构来提供。 可以形成填充层以填充开口，并且可以去除模具层，使得填充层保留在基底上。 可以形成间隔层，其在每个填充层的一侧填充彼此直接相邻的填充层之间的空间，并且在每个填充层的另一侧的每个填充层的侧壁处形成间隔物 层。 可以通过蚀刻由间隔层暴露的衬底来形成平行于多个栅极沟槽延伸的器件隔离沟槽。

    MOS transistors having recessed channel regions and methods of fabricating the same
    7.
    发明授权
    MOS transistors having recessed channel regions and methods of fabricating the same 失效
    具有凹陷沟道区的MOS晶体管及其制造方法

    公开(公告)号：US07750399B2

    公开(公告)日：2010-07-06

    申请号：US11957810

    申请日：2007-12-17

    申请人： Jay-Bok Choi

    发明人： Jay-Bok Choi

    IPC分类号： H01L29/94

    CPC分类号： H01L29/4236 ,  H01L29/1054 ,  H01L29/66621

    摘要： A MOS transistor having a recessed channel region is provided. A MOS transistor includes a source region and a drain region disposed in an active region of a semiconductor substrate and spaced apart from each other. A gate trench structure is disposed in the active region between the source and drain regions. A gate electrode is disposed in the gate trench structure. A gate dielectric layer is interposed between the gate trench structure and the gate electrode. A semiconductor region is disposed between the gate trench structure and the gate dielectric layer. The semiconductor region is formed of a different material from the active region. A method of fabricating the MOS transistor having a recessed channel region is also provided.

    摘要翻译： 提供具有凹陷沟道区的MOS晶体管。 MOS晶体管包括设置在半导体衬底的有源区域中并且彼此间隔开的源极区域和漏极区域。 栅极沟槽结构设置在源区和漏区之间的有源区中。 栅电极设置在栅极沟槽结构中。 栅极介电层插入在栅极沟槽结构和栅电极之间。 半导体区域设置在栅极沟槽结构和栅极介电层之间。 半导体区域由与活性区域不同的材料形成。 还提供了一种制造具有凹陷沟道区域的MOS晶体管的方法。

    SEMICONDUCTOR DEVICES
    9.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20120320655A1

    公开(公告)日：2012-12-20

    申请号：US13525675

    申请日：2012-06-18

    申请人： Seunguk Han ,  Jay-Bok Choi ,  Dong-Hyun Lee ,  Namho Jeon

    发明人： Seunguk Han ,  Jay-Bok Choi ,  Dong-Hyun Lee ,  Namho Jeon

    IPC分类号： G11C5/06

    CPC分类号： G11C5/025 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1116 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/1033 ,  H01L29/4238

    摘要： A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.

    摘要翻译： 半导体器件包括具有选择元件和数据存储元件的存储单元的单元区域，以及包括驱动晶体管的驱动电路区域，该驱动晶体管被配置为操作选择元件。 驱动晶体管包括由衬底中的器件隔离图案限定的有源部分和沿着第一方向跨过有源部分延伸的栅电极，栅电极包括环形结构的沟道部分。 驱动晶体管还包括设置在有源部分中的被沟道部分包围的第一杂质掺杂区域，以及设置在有源部分中的通过沟道部分与第一杂质掺杂区域分离的第二杂质掺杂区域。

    Semiconductor device having line-type trench to define active region and method of forming the same
    10.
    发明授权
    Semiconductor device having line-type trench to define active region and method of forming the same 有权
    具有线性沟槽以限定有源区的半导体器件及其形成方法

    公开(公告)号：US08729675B1

    公开(公告)日：2014-05-20

    申请号：US13763927

    申请日：2013-02-11

    申请人： Jay-Bok Choi ,  Kyu-Hyun Lee ,  Mi-Jeong Jang ,  Young-Jin Choi ,  Ju-Young Huh

    发明人： Jay-Bok Choi ,  Kyu-Hyun Lee ,  Mi-Jeong Jang ,  Young-Jin Choi ,  Ju-Young Huh

    IPC分类号： H01L29/40

    CPC分类号： H01L23/49838 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

    摘要翻译： 半导体器件包括彼此平行的多个平行沟槽，彼此平行的多个相交沟槽，由平行沟槽和交叉沟槽约束的多个有源区域，一个 穿过有源区的多个下导电线，彼此平行的多个上导线，穿过下导电线，并跨越有源区，以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。