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    Method of fabricating transistor of DRAM semiconductor device
    5.
    发明申请
    Method of fabricating transistor of DRAM semiconductor device 有权
    制造DRAM半导体器件晶体管的方法

    公开(公告)号：US20050042832A1

    公开(公告)日：2005-02-24

    申请号：US10922055

    申请日：2004-08-18

    申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/8242 ,  H01L29/51 ,  H01L21/3205 ,  H01L29/76 ,  H01L31/062

    CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

    摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

    摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

    Method of fabricating transistor of DRAM semiconductor device
    6.
    发明授权
    Method of fabricating transistor of DRAM semiconductor device 有权
    制造DRAM半导体器件晶体管的方法

    公开(公告)号：US07223649B2

    公开(公告)日：2007-05-29

    申请号：US10922055

    申请日：2004-08-18

    申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

    CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

    摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

    摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

    Method of forming fin field effect transistor
    8.
    发明授权
    Method of forming fin field effect transistor 有权
    形成鳍式场效应晶体管的方法

    公开(公告)号：US07056781B2

    公开(公告)日：2006-06-06

    申请号：US11014212

    申请日：2004-12-15

    申请人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

    发明人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78609

    摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

    摘要翻译： 根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。 在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。 侧壁由形成在器件隔离膜上的开口部分部分露出。 开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。 源极和漏极区域在栅电极不是的有源区域的一部分上。 可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

    Method of manufacturing a semiconductor device having a switching function
    9.
    发明授权
    Method of manufacturing a semiconductor device having a switching function 有权
    具有切换功能的半导体装置的制造方法

    公开(公告)号：US07297596B2

    公开(公告)日：2007-11-20

    申请号：US11552359

    申请日：2006-10-24

    申请人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

    发明人： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823437 ,  H01L21/823481

    摘要： A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

    Method of manufacturing a transistor
    10.
    发明授权
    Method of manufacturing a transistor 失效
    制造晶体管的方法

    公开(公告)号：US07265011B2

    公开(公告)日：2007-09-04

    申请号：US10898484

    申请日：2004-07-22

    申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

    摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

    摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。