A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.