Invention Grant
US09279673B2 Semiconductor device and method of calibrating warpage testing system to accurately measure semiconductor package warpage
有权
半导体器件和校准翘曲测试系统的方法,以准确测量半导体封装翘曲
- Patent Title: Semiconductor device and method of calibrating warpage testing system to accurately measure semiconductor package warpage
- Patent Title (中): 半导体器件和校准翘曲测试系统的方法,以准确测量半导体封装翘曲
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Application No.: US13846593Application Date: 2013-03-18
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Publication No.: US09279673B2Publication Date: 2016-03-08
- Inventor: WonJun Ko , SeungYong Chai , OhHan Kim , GwangTae Kim , Kenny Lee
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: G01K15/00
- IPC: G01K15/00 ; G01N25/72 ; G01N3/20 ; G01B11/30 ; H01L21/66

Abstract:
A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.
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