公开(公告)号：US09279673B2

公开(公告)日：2016-03-08

申请号：US13846593

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： WonJun Ko ,  SeungYong Chai ,  OhHan Kim ,  GwangTae Kim ,  Kenny Lee

IPC: G01K15/00 ,  G01N25/72 ,  G01N3/20 ,  G01B11/30 ,  H01L21/66

CPC classification number: G01B11/306 ,  H01L22/12

Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Abstract translation: 翘曲测试系统使用校准块在温度曲线上校准翘曲测试系统。 校准块包括结合到第二金属块的第一金属块。 第一金属块包括第一金属和第二不同的金属。 第一金属块包括与第二金属块的CTE不同的CTE。 校准块设置在翘曲测试系统中。 在28℃至260℃的温度曲线上测量校准块的翘曲。记录校准块的测量翘曲与校准块在温度曲线上的已知热膨胀之间的偏差。 半导体封装中的翘曲测量通过校准块的测量翘曲与校准块在温度曲线上的已知热膨胀或翘曲之间的偏差来补偿。

公开(公告)号：US20130256840A1

公开(公告)日：2013-10-03

申请号：US13906489

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： JaEun Yun ,  HunTeak Lee ,  SeungYong Chai ,  WonJun Ko

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/4805 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/11

Abstract: A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的积聚互连结构，该半导体晶片包含由锯街隔开的多个半导体管芯。 在互连结构上形成绝缘层。 在互连结构上形成凸起。 保护涂层材料沉积在绝缘层和锯条之上。 层压胶带涂在涂料上。 去除半导体晶片的背面的一部分。 安装带应用在背面上。 除去层压带，同时将涂层材料留在绝缘层和锯条上。 通过部分穿过半导体晶片延伸的锯条形成第一通道。 在形成第一通道之后去除涂层材料。 通过锯道形成第二通道，并且去除安装带以划分半导体晶片。

公开(公告)号：US20140269810A1

公开(公告)日：2014-09-18

申请号：US13846593

申请日：2013-03-18

Applicant: STATS CHIPPAC, LTD.

Inventor： WonJun Ko ,  SeungYong Chai ,  OhHan Kim ,  GwangTae Kim ,  Kenny Lee

IPC: G01N25/72

CPC classification number: G01B11/306 ,  H01L22/12

Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Abstract translation: 翘曲测试系统使用校准块在温度曲线上校准翘曲测试系统。 校准块包括结合到第二金属块的第一金属块。 第一金属块包括第一金属和第二不同的金属。 第一金属块包括与第二金属块的CTE不同的CTE。 校准块设置在翘曲测试系统中。 在28℃至260℃的温度曲线上测量校准块的翘曲。记录校准块的测量翘曲与校准块在温度曲线上的已知热膨胀之间的偏差。 半导体封装中的翘曲测量通过校准块的测量翘曲与校准块在温度曲线上的已知热膨胀或翘曲之间的偏差来补偿。