An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.