公开(公告)号：US20150022282A1

公开(公告)日：2015-01-22

申请号：US14331070

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Yuhei Kaneko ,  Kohei Nakamura

IPC: H03H11/28

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

Abstract translation: 阻抗调整电路包括将其计数值作为多个第一阻抗调整信号输出的计数器电路，将第二阻抗调整信号设定为处于活动/非活动状态而与计数值无关的模式选择电路，以及电平固定 电路将第三阻抗调整信号固定为处于活动状态。 响应于第一阻抗调整信号，第二阻抗调整信号和第三阻抗调节信号，预级电路分别产生多个第一输出控制信号，第二输出控制信号和第三输出控制信号， 和数据信号。 输出电路包括在输出端子和第一电源布线之间彼此并联连接的多个第一晶体管，第二晶体管和第三晶体管。 第一晶体管，第二晶体管和第三晶体管的控制端分别接收第一输出控制信号，第二输出控制信号和第三输出控制信号。

公开(公告)号：US09614497B2

公开(公告)日：2017-04-04

申请号：US15045124

申请日：2016-02-16

Applicant: Micron Technology, Inc.

Inventor： Yuhei Kaneko ,  Kohei Nakamura

IPC: H03K3/00 ,  H03H11/28 ,  H03H7/38 ,  H03K17/687

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

公开(公告)号：US09294072B2

公开(公告)日：2016-03-22

申请号：US14331070

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Yuhei Kaneko ,  Kohei Nakamura

IPC: H03H7/38 ,  H03H11/28

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

Abstract translation: 阻抗调整电路包括将其计数值作为多个第一阻抗调整信号输出的计数器电路，将第二阻抗调整信号设定为处于活动/非活动状态而与计数值无关的模式选择电路，以及电平固定 电路将第三阻抗调整信号固定为处于活动状态。 响应于第一阻抗调整信号，第二阻抗调整信号和第三阻抗调节信号，预级电路分别产生多个第一输出控制信号，第二输出控制信号和第三输出控制信号， 和数据信号。 输出电路包括在输出端子和第一电源布线之间彼此并联连接的多个第一晶体管，第二晶体管和第三晶体管。 第一晶体管，第二晶体管和第三晶体管的控制端分别接收第一输出控制信号，第二输出控制信号和第三输出控制信号。