公开(公告)号：US11164623B1

公开(公告)日：2021-11-02

申请号：US16903102

申请日：2020-06-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kohei Nakamura ,  Minari Arai

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C8/18 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22

Abstract: Apparatuses, systems, and methods for data strobe write timing. A memory device may receive a data strobe clock signal and serial write data during a write operation. A deserializer circuit of the memory may convert the serial write data into parallel write data using timing based on the data strobe clock signal. For example, one or more internal signals may be generated based on the data strobe clock signal and used to activate various operations of the deserializer circuit. The data strobe clock signal may also be used to activate bit lines of the memory device in order to write the parallel write data to memory cells along those activated bit lines. The memory may also receive a system clock, separate from the data strobe clock signal, which may be used for other operations of the memory. For example, in a read operation, the bit lines may be activated with timing based on the system clock.

公开(公告)号：US10734046B2

公开(公告)日：2020-08-04

申请号：US16436655

申请日：2019-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita ,  Shuichi Murai ,  Kohei Nakamura

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

公开(公告)号：US09294072B2

公开(公告)日：2016-03-22

申请号：US14331070

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Yuhei Kaneko ,  Kohei Nakamura

IPC: H03H7/38 ,  H03H11/28

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

Abstract translation: 阻抗调整电路包括将其计数值作为多个第一阻抗调整信号输出的计数器电路，将第二阻抗调整信号设定为处于活动/非活动状态而与计数值无关的模式选择电路，以及电平固定 电路将第三阻抗调整信号固定为处于活动状态。 响应于第一阻抗调整信号，第二阻抗调整信号和第三阻抗调节信号，预级电路分别产生多个第一输出控制信号，第二输出控制信号和第三输出控制信号， 和数据信号。 输出电路包括在输出端子和第一电源布线之间彼此并联连接的多个第一晶体管，第二晶体管和第三晶体管。 第一晶体管，第二晶体管和第三晶体管的控制端分别接收第一输出控制信号，第二输出控制信号和第三输出控制信号。

公开(公告)号：US20190304532A1

公开(公告)日：2019-10-03

申请号：US16444365

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/135 ,  H03K3/037 ,  H03K5/1534 ,  H03K5/05

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US10803923B2

公开(公告)日：2020-10-13

申请号：US16444365

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/1534 ,  H03K5/05 ,  H03K3/037 ,  H03K5/135 ,  G11C7/22 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US10418081B1

公开(公告)日：2019-09-17

申请号：US16156862

申请日：2018-10-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita ,  Shuichi Murai ,  Kohei Nakamura

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/15 ,  H03K5/00

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

公开(公告)号：US20240386942A1

公开(公告)日：2024-11-21

申请号：US18635854

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Nobuki Takahashi ,  Kohei Nakamura

IPC: G11C11/4093 ,  H03H11/04

Abstract: An example apparatus includes a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode. The plurality of transistors may include first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode. The plurality of transistors may further include third and fourth transistors connected in series between the first and second nodes and controlled in common by a second control signal activated in the second mode.

公开(公告)号：US09614497B2

公开(公告)日：2017-04-04

申请号：US15045124

申请日：2016-02-16

Applicant: Micron Technology, Inc.

Inventor： Yuhei Kaneko ,  Kohei Nakamura

IPC: H03K3/00 ,  H03H11/28 ,  H03H7/38 ,  H03K17/687

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

公开(公告)号：US20160164494A1

公开(公告)日：2016-06-09

申请号：US15045124

申请日：2016-02-16

Applicant: Micron Technology, Inc.

Inventor： YUHEI KANEKO ,  Kohei Nakamura

IPC: H03H11/28 ,  H03K17/687

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

公开(公告)号：US12283342B2

公开(公告)日：2025-04-22

申请号：US18055588

申请日：2022-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kohei Nakamura ,  Shuichi Tsukada

IPC: G11C7/10 ,  G11C7/02 ,  G11C7/14

Abstract: Apparatuses, systems, and methods for input buffer data feedback equalization (DFE). An input buffer includes a DFE circuit which adjusts a threshold voltage of the input buffer based on a previously latched data bit. The DFE circuit includes a number of DFE legs coupled in parallel to a node of the input buffer. Each DFE leg is selectively activated by a DFE code. Each DFE leg includes a capacitance (e.g., a field effect transistor) which is coupled to the node in an active leg based on the previously latched data bit. The previously latched data bit may also be used to generate a reset signal which couples the capacitors to ground. Each DFE leg may also include a transistor coupled to a bias voltage, which is stable across a range of PVT variations.