Invention Grant
US09299667B2 Method of shaping densely arranged PL gates and peripheral MOS gates for ILD oxide fill-in
有权
用于ILD氧化物填充的密集布置的PL栅极和外围MOS栅极的形成方法
- Patent Title: Method of shaping densely arranged PL gates and peripheral MOS gates for ILD oxide fill-in
- Patent Title (中): 用于ILD氧化物填充的密集布置的PL栅极和外围MOS栅极的形成方法
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Application No.: US14259771Application Date: 2014-04-23
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Publication No.: US09299667B2Publication Date: 2016-03-29
- Inventor: Fang-Hao Hsu , Shih-Ping Hong , Hong-Ji Lee
- Applicant: Macronix International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONICS INTERNATIONAL COMPANY, LTD.
- Current Assignee: MACRONICS INTERNATIONAL COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Stout, Uxa & Buyan, LLP
- Agent Frank J. Uxa
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/28 ; H01L23/00 ; H01L29/49
Abstract:
A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.
Public/Granted literature
- US20150311218A1 Method of Shaping Densely Arranged PL Gates and Peripheral MOS Gates for ILD Oxide Fill-In Public/Granted day:2015-10-29
Information query
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