公开(公告)号：US20160300761A1

公开(公告)日：2016-10-13

申请号：US14681988

申请日：2015-04-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Xin-Guan Lin ,  Hong-Ji Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76805 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53271

Abstract: A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.

Abstract translation: 提供一种制造半导体器件的方法。 介电层形成在阻挡层上。 在电介质层中形成第一开口并暴露阻挡层的一部分。 在第一开口的底部的阻挡层上形成保护层。 保护层在中心部分较厚，边缘部分较薄。 通过使用保护层作为掩模来去除暴露的阻挡层的一部分以形成第二开口。 第二开口具有邻近第二开口的侧壁设置在阻挡层中的至少一个子开口。 还提供了用该方法形成的半导体器件。

公开(公告)号：US09287285B2

公开(公告)日：2016-03-15

申请号：US14672777

申请日：2015-03-30

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L29/78 ,  H01L27/115 ,  H01L29/40 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

公开(公告)号：US20150228661A1

公开(公告)日：2015-08-13

申请号：US14672777

申请日：2015-03-30

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract translation: 公开了一种制备用于形成硅化物的半导体栅极的自对准方法，例如硅化钴（CoSi）层。 氮化硅（SiN）和低温氧化物（LTO）衬垫类型的沉积，具有突出结构的SiN衬垫防止在形成自对准源时损坏栅极。 未损坏的栅极适用于CoSi沉积。

公开(公告)号：US20190214402A1

公开(公告)日：2019-07-11

申请号：US15866132

申请日：2018-01-09

Applicant: MACRONIX International Co., Ltd.

Inventor： I-Ting Lin ,  Yuan-Chieh Chiu ,  Hong-Ji Lee

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L21/28 ,  G11C11/56 ,  G11C16/04 ,  G11C14/00 ,  G11C16/34

CPC classification number: H01L27/11578 ,  G11C11/5671 ,  G11C14/0018 ,  G11C16/0466 ,  G11C16/3422 ,  H01L27/1157 ,  H01L29/40117

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

公开(公告)号：US09881809B2

公开(公告)日：2018-01-30

申请号：US14681988

申请日：2015-04-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Xin-Guan Lin ,  Hong-Ji Lee

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/31111 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76805 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53271

Abstract: A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.

公开(公告)号：US09337036B2

公开(公告)日：2016-05-10

申请号：US14162737

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Hong-Ji Lee

IPC: H01L21/00 ,  H01L21/16 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/165 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02639 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76849

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract translation: 半导体制造中氧化铜形成的影响通过用硫化物等离子体蚀刻来缓解。 等离子体在铜表面形成保护性硫化铜膜，防止形成铜氧化物。 当发生铜氧化物形成时，硫化物等离子体能够将氧化铜转化为可接受或更导电的铜化合物。 使用清晰的湿条除去非氧化物铜化合物。

公开(公告)号：US10204859B2

公开(公告)日：2019-02-12

申请号：US15415699

申请日：2017-01-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Min-Hsuan Huang

IPC: H01L23/52 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/522

Abstract: An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of the conductive pattern is disposed on the substrate. The conductive pattern has a notch on each of two sidewalls of the bottom portion.

公开(公告)号：US09627247B2

公开(公告)日：2017-04-18

申请号：US14729843

申请日：2015-06-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L29/00 ,  H01L21/762 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/0649

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

公开(公告)号：US20160190061A1

公开(公告)日：2016-06-30

申请号：US14582935

申请日：2014-12-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Hsu-Sheng Yu

IPC: H01L23/522 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric layer is located on the substrate. The dielectric layer has a plurality of openings, and side walls of the openings have concave-and-convex profile.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括衬底和电介质层。 电介质层位于衬底上。 电介质层具有多个开口，开口的侧壁具有凹凸形状。

公开(公告)号：US09299667B2

公开(公告)日：2016-03-29

申请号：US14259771

申请日：2014-04-23

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Shih-Ping Hong ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/00 ,  H01L29/49

CPC classification number: H01L23/564 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract translation: 描述了一种促进集成电路的密集配置的阵列中的晶体管之间的层间电介质填充的方法。 公开了利用微加载效应以在晶体管之间产生T形轮廓的蚀刻工艺。 微载物对集成电路的外围区域中的晶体管具有可忽略的影响。