公开(公告)号：US09287285B2

公开(公告)日：2016-03-15

申请号：US14672777

申请日：2015-03-30

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L29/78 ,  H01L27/115 ,  H01L29/40 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

公开(公告)号：US20150228661A1

公开(公告)日：2015-08-13

申请号：US14672777

申请日：2015-03-30

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Zusing Yang ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/823835 ,  H01L27/11521 ,  H01L29/0684 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract translation: 公开了一种制备用于形成硅化物的半导体栅极的自对准方法，例如硅化钴（CoSi）层。 氮化硅（SiN）和低温氧化物（LTO）衬垫类型的沉积，具有突出结构的SiN衬垫防止在形成自对准源时损坏栅极。 未损坏的栅极适用于CoSi沉积。

公开(公告)号：US20160358810A1

公开(公告)日：2016-12-08

申请号：US14729843

申请日：2015-06-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/76229 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/0649

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

Abstract translation: 提供一种制造半导体器件的方法，包括以下。 在基板上形成第一材料层，第二材料层和掩模层。 通过以掩模层作为掩模执行第一蚀刻工艺来去除第二材料层的一部分，以暴露第一材料层并形成第一图案层和第二图案层。 通过以掩模层作为掩模进行第二蚀刻工艺来去除第一材料层的一部分，以暴露基板的一部分。 通过用掩模层作为掩模执行第三蚀刻工艺来去除衬底的一部分，以便形成第一沟槽和第二沟槽。 第二沟槽的侧壁和衬底的表面形成至少两个不同的角度。

公开(公告)号：US20150179569A1

公开(公告)日：2015-06-25

申请号：US14138007

申请日：2013-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hsu-Sheng Yu ,  Kuo-Feng Lo ,  Hong-Ji Lee

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract translation: 描述了形成在接触膜叠层中的接触孔中消除悬垂的方法。 衬垫层覆盖在接触膜叠层上，衬垫也涂覆接触孔。 衬里的一部分被去除以露出突出端，并且去除暴露的突出端。 衬套也用于填充接触孔的弯曲轮廓，从而使接触孔的侧壁平滑和直线适于金属填充，同时抑制管道缺陷。

公开(公告)号：US09425086B2

公开(公告)日：2016-08-23

申请号：US14138007

申请日：2013-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hsu-Sheng Yu ,  Kuo-Feng Lo ,  Hong-Ji Lee

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract translation: 描述了形成在接触膜叠层中的接触孔中消除悬垂的方法。 衬垫层覆盖在接触膜叠层上，衬垫也涂覆接触孔。 衬里的一部分被去除以露出突出端，并且去除暴露的突出端。 衬套也用于填充接触孔的弯曲轮廓，从而使接触孔的侧壁平滑和直线适于金属填充，同时抑制管道缺陷。

公开(公告)号：US20160064479A1

公开(公告)日：2016-03-03

申请号：US14468832

申请日：2014-08-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first dielectric layer, a first conductive layer, and an isolation structure. The substrate has a trench. The first dielectric layer is disposed on the substrate between two neighboring trenches. The first conductive layer is disposed on the first dielectric layer. The isolation structure, including a step zone and a recessed zone, is disposed in the trench, wherein an upper surface of the step zone is higher than an upper surface of the first dielectric layer.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括衬底，第一介电层，第一导电层和隔离结构。 衬底具有沟槽。 第一电介质层设置在两个相邻沟槽之间的衬底上。 第一导电层设置在第一介电层上。 包括阶梯区和凹陷区的隔离结构设置在沟槽中，其中台阶区的上表面高于第一介电层的上表面。

公开(公告)号：US09224803B2

公开(公告)日：2015-12-29

申请号：US13875998

申请日：2013-05-02

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L23/58 ,  H01L29/06 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L29/06 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract translation: 通过使用其中形成有沟槽的阻挡层形成具有大纵横比的小接触孔。 在沟槽上方形成较大的接触孔，并利用沟槽和阻挡层的特性形成小沟槽下方的小接触孔，以限制小接触孔的尺寸。

公开(公告)号：US20150311218A1

公开(公告)日：2015-10-29

申请号：US14259771

申请日：2014-04-23

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Shih-Ping Hong ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/00 ,  H01L29/49

CPC classification number: H01L23/564 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract translation: 描述了一种促进集成电路的密集配置的阵列中的晶体管之间的层间电介质填充的方法。 公开了利用微载荷效应在晶体管之间产生T形轮廓的蚀刻工艺。 微载物对集成电路的外围区域中的晶体管具有可忽略的影响。

公开(公告)号：US09627247B2

公开(公告)日：2017-04-18

申请号：US14729843

申请日：2015-06-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L29/00 ,  H01L21/762 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/0649

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

公开(公告)号：US09299667B2

公开(公告)日：2016-03-29

申请号：US14259771

申请日：2014-04-23

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Shih-Ping Hong ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/00 ,  H01L29/49

CPC classification number: H01L23/564 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract translation: 描述了一种促进集成电路的密集配置的阵列中的晶体管之间的层间电介质填充的方法。 公开了利用微加载效应以在晶体管之间产生T形轮廓的蚀刻工艺。 微载物对集成电路的外围区域中的晶体管具有可忽略的影响。