Invention Grant
US09304954B2 Multi processor bridge with mixed Endian mode support 有权
具有混合端模式支持的多处理器桥

Multi processor bridge with mixed Endian mode support
Abstract:
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.
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