Invention Grant
- Patent Title: Multi processor bridge with mixed Endian mode support
- Patent Title (中): 具有混合端模式支持的多处理器桥
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Application No.: US14031567Application Date: 2013-09-19
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Publication No.: US09304954B2Publication Date: 2016-04-05
- Inventor: Daniel B Wu , Matthew D Pierson , Kai Chirca
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/16 ; G06F13/40 ; G06F12/08

Abstract:
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.
Public/Granted literature
- US20140115270A1 MULTI PROCESSOR BRIDGE WITH MIXED ENDIAN MODE SUPPORT Public/Granted day:2014-04-24
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